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12-bit, 20 msps/40 msps/65 msps 3 v low power a/d converter ad9237 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005C2010 analog devices, inc. all rights reserved. features ultralow power 85 mw at 20 msps 135 mw at 40 msps 190 mw at 65 msps snr = 66 dbc to nyquist at 65 msps sfdr = 80 dbc to nyquist at 65 msps dnl = 0.7 lsb differential input with 500 mhz bandwidth flexible analog input: 1 v p-p to 4 v p-p range offset binary, twos complement, or gray code data formats output enable pin 2-step power-down full power-down and sleep mode clock duty cycle stabilizer applications ultrasound and medical imaging battery-powered instruments hand-held scope meters low cost digital oscilloscopes low power digital still cameras and copiers low power communications functional block diagram sha vin+ vin? drvdd clk pdwn mode clock duty cycle stabilizer mode select dgnd otr d11 d0 avdd mdac1 correction logic output buffers ref select agnd 0.5v vref sense ad9237 05455-001 reft refb mode2 a/d a/d 4 15 12 3 oe 10-stage 1 1/2-bit pipeline figure 1. general description the ad9237 is a family of monolithic, single 3 v supply, 12-bit, 20 msps/40 msps/65 msps analog-to-digital converters (adc). this family features a high performance sample-and- hold amplifier (sha) and voltage reference. the ad9237 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20 msps/ 40 msps/65 msps data rates and guarantees no missing codes over the full operating temperature range. with significant power savings over previously available adcs, the ad9237 is suitable for applications in imaging and medical ultrasound. fabricated on an advanced cmos process, the ad9237 is available in a 32-lead lfcsp and is specified over the industrial temperature range (?40c to +85c). product highlights 1. operating at 65 msps, the ad9237 consumes a low 190 mw at 65 msps, 135 mw at 40 msps, and 85 mw at 20 msps. 2. power scaling reduces the operating power further when running at lower speeds. 3. the ad9237 operates from a single 3 v power supply and features a separate digital output driver supply to accommodate 2.5 v and 3.3 v logic families. 4. the patented sha input maintains excellent performance for input frequencies beyond nyquist and can be configured for single-ended or differential operation. 5. the ad9237 is optimized for selectable and flexible input ranges from 1 v p-p to 4 v p-p. 6. an output enable pin allows for multiplexing of the outputs. 7. two-step power-down supports a standby mode in addition to a power-down mode. 8. the otr output bit indicates when the signal is beyond the selected input range. 9. the clock duty cycle stabilizer (dcs) maintains converter performance over a wide range of clock pulse widths.
ad9237 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? digital specifications ................................................................... 4 ? ac specifications .......................................................................... 4 ? switching specifications .............................................................. 5 ? timing diagram ............................................................................... 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ..............................8 ? terminology .......................................................................................9 ? equivalent circuits ......................................................................... 10 ? typical performance characteristics ........................................... 11 ? applying the ad9237 .................................................................... 16 ? theory of operation .................................................................. 16 ? analog input and reference overview ................................... 16 ? voltage reference ....................................................................... 18 ? clock input considerations ...................................................... 19 ? power dissipation, power scaling, and standby mode ......... 19 ? digital outputs ........................................................................... 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 5/10rev. 0 to rev. a changes to product highlights section ......................................... 1 changes to pipeline delay parameter in table 4 .......................... 5 changes to figure 2 .......................................................................... 6 changes to figure 3 and table 6 ..................................................... 8 10/05revision 0: initial version
ad9237 rev. a | page 3 of 24 specifications dc specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, ?0.5 dbfs input, 1.0 v internal reference, t min to t max , unless otherwise noted. table 1. ad9237bcp-20 ad9237bcp-40 ad9237bcp-65 parameter min typ max min typ max min typ max unit resolution 12 12 12 bits accuracy no missing codes guaranteed 12 12 12 bits offset error 1.30 1.95 1.30 1.95 1.30 1.95 % fsr gain error 1 0.70 2.10 0.75 2.10 1.05 2.25 % fsr differential nonlinearity (dnl) 2 0.70 0.95 0.70 0.95 ?1.00 0.70 +1.25 lsb integral nonlinearity (inl) 2 0.90 1.35 0.90 1.35 0.90 2.00 lsb temperature drift offset error 2 2 2 ppm/c gain error 1 12 12 12 ppm/c internal voltage reference output voltage error (1 v mode) 5 25 5 25 5 25 mv load regulation @ 1.0 ma 0.8 0.8 0.8 mv output voltage error (0.5 v mode) 2.5 2.5 2.5 mv load regulation @ 0.5 ma 0.1 0.1 0.1 mv reference input resistance 7 7 7 k input referred noise vref = 0.5 v 1.35 1.35 1.35 lsb rms vref = 1.0 v 0.70 0.70 0.70 lsb rms analog input input span vref = 0.5 v; mode2 = 0 v 1 1 1 v p-p vref = 1.0 v; mode2 = 0 v 2 2 2 v p-p vref = 0.5 v; mode2 = avdd 2 2 2 v p-p vref = 1.0 v; mode2 = avdd 4 4 4 v p-p input capacitance 3 7 7 7 pf power supplies supply voltages avdd 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 v supply current iavdd 2 30.5 45.5 64.5 ma idrvdd 2 3.0 4.5 5.5 ma psrr 0.01 0.01 0.01 % fsr power consumption dc input 4 85 135 190 mw sine wave input 2 100 120 150 180 210 270 mw power-down mode 1 1 1 mw standby power 20 20 20 mw 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate, f in = 2.4 mhz, full-scale sine wave, with approx imately 5 pf loading on each output bit. 3 input capacitance refers to the effectiv e capacitance between one differential input pin and agnd. refer to for the e quivalent analog input structure. figure 4 4 measured with dc input at maximum clock rate.
ad9237 rev. a | page 4 of 24 digital specifications table 2. ad9237bcp-20 ad9237bcp-40 ad9237bcp-65 parameter min typ max min typ max min typ max unit logic inputs high level input voltage 2.0 2.0 2.0 v low level input voltage 0.8 0.8 0.8 v high level input current C10 +10 C10 +10 C10 +10 a low level input current C10 +10 C10 +10 C10 +10 a input capacitance 2 2 2 pf logic outputs 1 drvdd = 3.3 v high-level output voltage (ioh = 50 a) 3.29 3.29 3.29 v high-level output voltage (ioh = 0.5 ma) 3.25 3.25 3.25 v low-level output voltage (iol = 1.6 ma) 0.2 0.2 0.2 v low-level output voltage (iol = 50 a) 0.05 0.05 0.05 v drvdd = 2.5 v high-level output voltage (ioh = 50 a) 2.49 2.49 2.49 v high-level output voltage (ioh = 0.5 ma) 2.45 2.45 2.45 v low-level output voltage (iol = 1.6 ma) 0.2 0.2 0.2 v low-level output voltage (iol = 50 a) 0.05 0.05 0.05 v 1 output voltage levels measured with 5 pf load on each output. ac specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, a in = C0.5 dbfs, 1.0 v internal reference, t min to t max , unless otherwise noted. table 3. ad9237bcp-20 ad9237bcp-40 ad9237bcp-65 parameter min typ max min typ max min typ max unit signal-to-noise ratio (snr) f input = 2.4 mhz 66.8 66.5 66.5 dbc f input = 9.7 mhz 65.6 66.6 dbc f input = 19.6 mhz 65.3 66.6 dbc f input = 34.2 mhz 64.0 66.1 dbc f input = 70 mhz 66.0 66.3 65.9 dbc signal-to-noise ratio and distortion (sinad) f input = 2.4 mhz 66.7 66.4 66.3 dbc f input = 9.7 mhz 65.1 66.5 dbc f input = 19.6 mhz 64.4 66.4 dbc f input = 34.2 mhz 63.5 65.8 dbc f input = 70 mhz 65.6 65.8 65.2 dbc effective number of bits (enob) f input = 9.7 mhz 10.8 bits f input = 19.6 mhz 10.7 bits f input = 34.2 mhz 10.6 bits
ad9237 rev. a | page 5 of 24 ad9237bcp-20 ad9237bcp-40 ad9237bcp-65 parameter min typ max min typ max min typ max unit spurious-free dynamic range (sfdr) f input = 2.4 mhz 88.0 83.5 85.5 dbc f input = 9.7 mhz 72.4 87.5 dbc f input = 19.6 mhz 72.2 82.4 dbc f input = 34.2 mhz 69.4 80.1 dbc f input = 70 mhz 80.5 77.9 74.9 dbc worst harmonic (second or third) f input = 2.4 mhz ?88.0 ?83.5 ?85.5 dbc f input = 9.7 mhz ?72.4 ?87.5 dbc f input = 19.6 mhz ?72.2 ?82.4 dbc f input = 34.2 mhz ?69.4 ?80.1 dbc f input = 70 mhz ?80.5 ?77.9 ?74.9 dbc worst other spur f input = 2.4 mhz ?90 ?90 ?90 dbc f input = 9.7 mhz ?73.4 ?90 dbc f input = 19.6 mhz ?73.1 ?90 dbc f input = 34.2 mhz ?72.0 ?90 dbc f input = 70 mhz ?90 ?90 ?90 dbc switching specifications table 4. ad9237bcp-20 ad9237bcp-40 ad9237bcp-65 parameter min typ max min typ max min typ max unit clk input parameters maximum conversion rate 20 40 65 msps minimum conversion rate 1 1 1 msps clk period 50.0 25.0 15.4 ns clk pulse width high 1 15.0 8.8 6.2 ns clk pulse width low 1 15.0 8.8 6.2 ns data output parameters output delay (t pd ) 2 3.5 3.5 3.5 ns pipeline delay (latency) 9 9 9 cycles output enable time 6 6 6 ns output disable time 3 3 3 ns aperture delay (t a ) 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) 0.5 0.5 0.5 ps rms wake-up time (sleep mode) 3 3.0 3.0 3.0 ms wake-up time (standby mode) 3 3.0 3.0 3.0 s out-of-range recovery time 1 1 2 cycles 1 with duty cycle stabilizer enabled. 2 output delay is measured from clk 50% transition to data 50% transition, with 5 pf load on each output. 3 wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 f and 10 f capacitors on reft and refb.
ad9237 rev. a | page 6 of 24 timing diagram n?10 n?9 n?8 n?7 n?6 n?5 n?4 n?3 n?2 n?1 analog input clk data out n?1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n?11 t pd t a 05455-002 figure 2. timing diagram
ad9237 rev. a | page 7 of 24 absolute maximum ratings table 5. pin name with respect to min max unit electrical avdd agnd C0.3 +3.9 v drvdd dgnd C0.3 +3.9 v agnd dgnd C0.3 +0.3 v avdd drvdd C3.9 +3.9 v digital outputs, oe dgnd C0.3 drvdd + 0.3 v clk, mode, mode2 agnd ?0.3 avdd + 0.3 v vin+, vinC agnd C0.3 avdd + 0.3 v vref agnd C0.3 avdd + 0.3 v sense agnd C0.3 avdd + 0.3 v refb, reft agnd C0.3 avdd + 0.3 v pdwn agnd C0.3 avdd + 0.3 v environmental 1 operating temperature C40 +85 c junction temperature 150 c lead temperature (10 sec) 300 c storage temperature C65 +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. esd caution 1 typical thermal impedances (32-lead lfcsp), ja = 32.5c/w, jc = 32.71c/w. these measurements were taken on a 4-la yer board in still air, in accordance with eia/jesd51-1.
ad9237 rev. a | page 8 of 24 pin configuration and fu nction descriptions 05455-003 notes 1. dnc = do not connect. 2. it is recommended that the exposed paddle be soldered to the ground plane. pin 1 indicator 1 mode2 2 clk 3 oe 4 pdwn 5 gc 6 dnc 7 d0 (lsb) 8 d1 24 vref 23 sense 22 mode 21 otr 20 d11 (msb) 19 d10 18 d9 17 d8 9 d2 10 d3 11 d4 12 d5 13 d6 14 d7 15 dgnd 16 drvdd 32 av dd 31 agnd 30 vin? 29 vin+ 28 agnd 27 avdd 26 reft 25 refb top view (not to scale) ad9237 figure 3. pin configuration table 6. pin function descriptions pin number mnemonic description 1 mode2 sha gain select an d power scaling control (see table 8 ). 2 clk clock input pin. 3 oe output enable pin (active low). 4 pdwn power-down function selection (see table 9 ). 5 gc gray code control (active high). 6 dnc do not connect. 7 to 14, 17 to 20 d0 (lsb) to d11 (msb) data output bits. 15 dgnd digital output ground. 16 drvdd digital output driver supply. must be decouple d to dgnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f in parallel with 10 f. 21 otr out-of-range indicator. 22 mode data format and clock duty cycle stabilizer (dcs) mode selection (see table 10 ). 23 sense reference mode selection (see table 7 ). 24 vref voltage reference input/output (see table 7 ). 25 refb differential reference (?). must be deco upled to reft with a minimum 10 f capacitor. 26 reft differential reference (+). 27, 32 avdd analog power supply. must be decoupled to agnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f in parallel with 10 f. 28, 31 agnd analog ground. 29 vin+ analog input pin (+). 30 vin? analog input pin (?). ep it is recommended that the exposed paddle be soldered to the ground plane. there is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board.
ad9237 rev. a | page 9 of 24 terminology analog bandwidth (full power bandwidth) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay (t a ) the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture jitter (t j ) the sample-to-sample variation in aperture delay. integral nonlinearity (inl) the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsbs beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. offset error the major carry transition should occur for an analog value ? lsb below vin+ = vinC. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value ? lsb above negative full scale. the last transition should occur at an analog value 1? lsb below the positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temp er atu re d r i f t the temperature drift for offset error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . power supply rejection ratio the change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. total harmonic distortion (thd) 1 the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. signal-to-noise and distortion (sinad) 1 the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. effective number of bits (enob) the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad using the following formula: enob = ( sinad dbfs ? 1.76)/6.02 signal-to-noise ratio (snr) 1 the ratio of the rms signal to the rms value of the sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. spurious-free dynamic range (sfdr) 1 sfdr is the difference in db between the rms amplitude of the input signal and the rms value of the peak spurious signal. the peak spurious signal may not be an harmonic. two-tone sfdr 1 the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. clock pulse width and duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated performance. pulse width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these specifications define an acceptable clock duty cycle. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay (t pd ) the delay between the clock logic threshold and the time when all bits are within valid logic levels. out-of-range recovery time the time it takes the adc to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. 1 ac specifications may be reported in dbc (degrades as signal levels are lowered) or in dbfs (always related back to converter full scale).
ad9237 rev. a | page 10 of 24 equivalent circuits 05455-004 avdd v in+, vin? figure 4. equivalent analog input circuit 05455-005 mode, mode2, gc, oe 375 70k figure 5. equivalent mode, mode2, gc, oe input circuit d11?d0, otr drvdd 05455-006 figure 6. equivalent digital output circuit 05455-007 clk, pdwn 375 figure 7. equivalent clk, pdwn input circuit
ad9237 rev. a | page 11 of 24 typical performance characteristics avdd = 3.0 v, drvdd = 2.5 v, maximum sample rate with dcs disabled, t a = 25c, 2 v p-p differential input, a in = C0.5 dbfs, vref = 1.0 v internal, fft length 16 k, unless otherwise noted. frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 01 68 4 2 05455-008 0 snr = 66.9dbc sfdr = 87.0dbc figure 8. ad9237-20 10 mhz fft frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 02 0 snr = 66.8dbc sfdr = 83.1dbc 12 16 8 41 8 10 14 6 2 05455-009 figure 9. ad9237-40 20 mhz fft frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 05455-010 snr = 66.0dbc sfdr = 78.6dbc 0 30 32.5 25 20 15 10 5 figure 10. ad9237-65 70 mhz fft clock frequency (msps) snr/sfdr (dbc) 90 85 80 75 70 65 60 10.0 20.0 17.5 15.0 12.5 05455-011 snr sfdr figure 11. ad9237-20 snr/sfdr vs. clock frequency with f in = 10 mhz clock frequency (msps) snr/sfdr (dbc) 90 85 80 75 sfdr snr 70 65 20 40 35 30 25 05455-012 figure 12. ad9237-40 snr/sfdr vs. clock frequency with f in = 20 mhz clock frequency (msps) snr/sfdr (dbc) 90 85 80 75 70 65 60 40 65 55 60 50 45 05455-013 snr sfdr figure 13. ad9237-65 snr/sfdr vs. clock frequency with f in = 35 mhz
ad9237 rev. a | page 12 of 24 frequency (mhz) amplitude (dbc) 0 ?120 ?100 ?80 ?60 ?40 ?20 snr = 65.6dbc sfdr = 67.1dbc 05455-014 0 30 32.5 25 20 15 10 5 figure 14. ad9237-65 100 mhz fft input amplitude (dbfs) snr/sfdr (dbc and dbfs) 90 80 70 60 50 40 30 ?30 0 ?5 ?10 ?15 ?20 ?25 05455-017 sfdr dbfs 4v p-p sfdr dbc 4v p-p snr dbfs 2v p-p snr dbfs 4v p-p snr dbc 2v p-p snr dbc 4v p-p sfdr dbfs 2v p-p sfdr dbc 2v p-p figure 15. ad9237-65 snr/sfdr vs. input amplitude with f in = 35 mhz input amplitude (dbfs) snr/sfdr (dbc and dbfs) 100 90 80 70 60 50 40 30 ?30 0 ?5 ?10 ?15 ?20 ?25 05455-019 sfdr dbfs 2v p-p snr dbc 2v p-p snr dbc 1v p-p sfdr dbfs 1v p-p sfdr dbc 2v p-p sfdr dbc 1v p-p snr dbfs 2v p-p snr dbfs 1v p-p figure 16. ad9237-40 snr/sfdr vs. input amplitude with f in = 20 mhz duty cycle (%) snr/sfdr (dbc) 90 50 55 60 65 70 75 80 85 30 7065605550454035 05455-030 sfdr dcs enabled sfdr dcs disabled snr dcs enabled snr dcs disabled figure 17. snr/sfdr vs. clock duty cycle input amplitude (dbfs) snr/sfdr (dbc and dbfs) 90 80 70 60 50 40 30 ?30 0 ?5 ?10 ?15 ?20 ?25 05455-018 sfdr dbfs 2v p-p snr dbfs 2v p-p snr dbfs 1v p-p snr dbc 2v p-p snr dbc 1v p-p sfdr dbc 2v p-p sfdr dbc 1v p-p sfdr dbfs 1v p-p figure 18. ad9237-65 snr/sfdr vs. input amplitude with f in = 35 mhz input amplitude (dbfs) snr/sfdr (dbc and dbfs) 100 90 80 70 60 50 40 30 ?30 0 ?5 ?10 ?15 ?20 ?25 05455-020 sfdr dbfs 2v p-p snr dbc 2v p-p snr dbc 1v p-p sfdr dbfs 1v p-p sfdr dbc 2v p-p sfdr dbc 1v p-p snr dbfs 2v p-p snr dbfs 1v p-p figure 19. ad9237-20 snr/sfdr vs. input amplitude with f in = 10 mhz
ad9237 rev. a | page 13 of 24 frequency (mhz) amplitude (dbc) 0 ?20 ?40 ?60 ?80 ?100 ?120 0 30 32.5 25 20 15 10 5 05455-095 snr = 67.0dbfs sfdr = 87.8dbfs figure 20. ad9237-65 two-tone fft, f in1 = 45 mhz, f in2 = 46 mhz frequency (mhz) amplitude (dbc) 0 ?20 ?40 ?60 ?80 ?100 ?120 02 15 10 5 05455-021 0 snr = 67.2dbfs sfdr = 88.3dbfs figure 21. ad9237-40 two-tone fft f in1 = 45 mhz, f in2 = 46 mhz frequency (mhz) amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 03 25 20 15 10 5 05455-094 0 snr = 66.9dbfs sfdr = 84.1dbfs figure 22. ad9237-65 two-tone fft, f in1 = 69 mhz, f in2 = 70 mhz sfdr dbfs sfdr dbc snr dbc input amplitude (ain) snr/sfdr (dbc and dbfs) 100 30 40 50 60 70 80 90 ?30 ?10 ?6.5 ?15 ?20 ?25 05455-024 snr dbfs figure 23. ad9237-65 two-tone sn r/sfdr , vs. analog input with f in1 = 45 mhz, f in2 = 46 mhz sfdr dbfs sfdr dbc snr dbc input amplitude (ain) snr/sfdr (dbc and dbfs) 100 30 40 50 60 70 80 90 ?30 ?10 ?6.5 ?15 ?20 ?25 05455-025 snr dbfs figure 24. ad9237-40 two-tone sn r/sfdr , vs. analog input with f in1 = 45 mhz, f in2 = 46 mhz sfdr dbfs sfdr dbc snr dbc input amplitude (ain) snr/sfdr (dbc and dbfs) 100 30 40 50 60 70 80 90 ?30 ?10 ?6.5 ?15 ?20 ?25 05455-098 snr dbfs figure 25. ad9237-65 two-tone snr/sfdr vs. analog input with f in1 = 69 mhz, f in2 = 70 mhz
ad9237 rev. a | page 14 of 24 frequency (mhz) amplitude (dbc) 0 ?20 ?40 ?60 ?80 ?100 ?120 02 15 10 5 05455-026 0 snr = 67.1dbfs sfdr = 87.3dbfs figure 26. ad9237-40 two-tone fft f in1 = 69 mhz, f in2 = 70 mhz input frequency (mhz) snr/sfdr (dbc) 90 85 80 sfdr snr 75 70 60 65 55 0 125 100 75 50 25 05455-015 figure 27. ad9237-65 snr/sfdr vs. input frequency code inl (lsb) 1.00 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 0 4096 3584 3072 2560 2048 1536 1024 512 05455-032 figure 28. typical inl sfdr dbfs sfdr dbc snr dbc input amplitude (ain) snr/sfdr (dbc and dbfs) 100 30 40 50 60 70 80 90 ?30 ?10 ?6.5 ?15 ?20 ?25 05455-097 snr dbfs figure 29. ad9237-40 two-tone snr/sfdr vs. analog input with f in1 = 69 mhz, f in2 = 70 mhz input frequency (mhz) snr/sfdr (dbc) 90 55 60 65 70 75 80 85 0 125 100 75 50 25 05455-016 sfdr snr figure 30. ad9237-40 snr/sfdr vs. input frequency code dnl (lsb) 1.00 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 0 4096 3584 3072 2560 2048 1536 1024 512 05455-035 figure 31. typical dnl
ad9237 rev. a | page 15 of 24 clock frequency (msps) sinad (dbc) enob (bits) 67.5 67.0 66.5 66.0 65.5 65.0 10.83 10.75 10.67 10.59 10.50 10 20 70 60 50 40 30 05455-062 ad9237-40 ad9237-65 ad9237-20 figure 32. ad9237 sinad/enob vs. clock frequency with f in = nyquist temperature (c) snr/sfdr (dbc) 90 snr sfdr 85 80 75 70 65 60 ?40 ?20 8580 60 40 20 0 05455-063 figure 33. ad9237-65 snr/sfdr vs. temperature with f in = 32.5mhz
ad9237 rev. a | page 16 of 24 applying the ad9237 theory of operation the ad9237 uses a calibrated, 11-stage pipeline architecture with a patented input sha implemented. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor digital-to-analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage consists of a flash adc. the pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. while the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and to appear at the output, as shown in figure 2 . the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended modes. the output- staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down and stand-by operation, the output buffers go into a high impedance state. the adc samples the analog input on the rising edge of the clock. system disturbances just prior to, or immediately following, the rising edge of the clock and/or excessive clock jitter can cause the sha to acquire the wrong input value and should be minimized. analog input and reference overview the analog input to the ad9237 is a differential switched capacitor sha that has been designed for optimum performance while processing a differential input signal. the sha input can support a wide common-mode range and maintain excellent performance, as shown in figure 34 . an input common-mode voltage of midsupply minimizes signal-dependant errors and provides optimum performance. figure 35 shows the clock signal alternately switching the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. input common-mode level (v) snr/sfdr (dbc) 90 80 70 60 50 40 30 0 3.0 2.5 2.0 1.5 1.0 0.5 05455-038 2.5mhz sfdr 34.2mhz sfdr 2.5mhz snr 34.2mhz snr figure 34. ad9237-65 snr/sfdr vs. input common-mode level in addition, a small shunt capacitor placed across the inputs provides dynamic charging currents. this passive network creates a low-pass filter at the adcs input; therefore, the precise values are dependent on the application. in if under- sampling applications, the shunt capacitor(s) should be reduced or removed depending on the input frequency. in combination with the driving source impedance, the capacitors limit the input bandwidth. 05455-039 v in+ v in? c par c par 5pf 5pf t t h t t h figure 35. switched-c apacitor sha input for best dynamic performance, the source impedances driving vin+ and vinC should be matched so that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. an internal differential reference buffer creates positive and negative reference voltages, reft and refb, that define the span of the adc core.
ad9237 rev. a | page 17 of 24 the output common mode of the reference buffer is set to mid- supply, and the reft and refb voltages and input span are defined as: reft = ?( avdd + vref) refb = ?( avdd ? vref) () factor span vref factor span refb reft span _ 4 _ 4 = ? = the previous equations show that the reft and refb voltages are symmetrical about the midsupply voltage, and the input span is proportional to the value of the vref voltage, see table 7 for more details. the internal voltage reference can be pin strapped to fixed values of 0.5 v or 1.0 v, or adjusted within this range as discussed in the internal reference connection section. maximum snr performance is achieved with the ad9237 set to an input span of 2 v p-p or greater. the relative snr degradation is 3 db when changing from 2 v p-p mode to 1 v p-p mode. the sha must be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. the minimum and maximum common-mode input levels are defined as: vcm min = vref /2 vcm max = ( avdd + vref )/2 the minimum common-mode input level allows the ad9237 to accommodate ground-referenced inputs. although optimum performance is achieved with a differential input, a single-ended source can be driven into vin+ or vinC. in this configuration, one input accepts the signal while the opposite input should be set to midscale by connecting it to an appropriate reference. for example, a 2 v p-p signal can be applied to vin+ while a 1 v reference is applied to vinC. the ad9237 then accepts an input signal varying between 2 v and 0 v. in the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect is less noticeable at lower input frequencies and in the lower speed grade models (ad9237-40 and ad9237-20). differential input configurations as previously detailed, optimum performance is achieved while driving the ad9237 in a differential input configuration. for baseband applications, the ad8351 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8351 is easily set to avdd/2, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. figure 36 details a typical configuration using the ad8351. 05455-041 ad8351 ad9237 vin+ avdd agnd vin? ? + 33 1k 0.1 f 0.1 f 33 15pf 0.1 f 0.1 f 1.2k 25 1k 49.9 25 2 v p-p figure 36. differential input configuration using the ad8351 at input frequencies in the second nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the ad9237. this is especially true in if undersampling applications where frequencies in the 70 mhz to 100 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration, as shown in figure 37 . 05455-042 ad9237 vin+ avdd agnd vin? 33 0.1 f 33 15pf 1k 1k 2v p-p 49.9 the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few mhz, and excessive signal power can cause core saturation, which leads to distortion. single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, there is degradation in sfdr and distortion performance due to the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. figure 38 details a typical single- ended input configuration. 05455-099 ad9237 vin+ avdd agnd vin? 33 0.1 f 33 15pf 1k 1k 1k 1k 25 0.1 f 49.9 2 v p-p figure 38. single-ended input configuration
ad9237 rev. a | page 18 of 24 table 7. reference configuration summary selected mode sense voltage resulting vref (v) span factor resulting differential span (v p-p) external reference avdd n/a 2 factor span reference external 1 internal fixed reference vref 0.5 2 1.0 v 1 4.0 v programmable reference 0.2 v to vref 0.5 (1 + r2/r1) (see figure 40 ) 2 factor span vref 1 internal fixed reference agnd to 0.2 v 1.0 2 2.0 v 1 1.0 v voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9237. the input range can be adjusted by varying the reference voltage applied to the ad9237, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. in all reference configurations, reft and refb drive the a/d conversion core and, in conjunction with the span factor, establish its input span. the input range of the adc always equals four times the voltage at the reference pin divided by the span factor for either an internal or an external reference. it is required to decouple reft to refb with 0.1 f and 10 f decoupling capacitors, as shown in figure 39 . internal reference connection a comparator within the ad9237 detects the potential at the sense pin and configures the reference into one of four possible states, which are summarized in tabl e 7 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider, setting vref to 1 v (see figure 39 ). connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected, as shown in figure 40 , then the switch is again set to the sense pin. this puts the reference amplifier in a non- inverting mode with the vref output defined as ? ? ? ? ? ? += r r .vref 05455-043 adc core vin? sense vref vin+ reft refb 0.1 f 0.1 f 0.1 f 10 f + 0.5v select logic 0.1 f + 10 f ad9237 figure 39. internal reference configuration 05455-044 adc core vin? sense r2 r1 vref vin+ reft refb 0.1 f 0.1 f 0.1 f 10 f + 0.5v select logic 0.1 f + 10 f ad9237 figure 40. programmable reference configuration
ad9237 rev. a | page 19 of 24 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift characteristics. figure 41 shows the typical drift characteristics of the internal reference in both 1 v and 0.5 v modes. when multiple adcs track one another, a single reference (internal or external) reduces gain matching errors. when the sense pin is connected to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7 k load. the internal buffer still generates the positive and negative full-scale references, reft and refb, for the adc core. the input span is always four times the value of the reference voltage divided by the span factor; therefore, the external reference must be limited to a maximum of 1 v. temperature (c) vref error (%) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?40 ?20 8580 60 40 20 0 05455-046 1v reference 0.5v reference figure 41. typical vref drift if the internal reference of the ad9237 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. figure 42 shows how the internal reference voltage is affected by loading. a 2 ma load is the maximum recommended load. load (ma) error (%) 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 0 3.0 2.5 2.0 1.5 1.0 0.5 05455-093 0.5v error (%) 1v error (%) figure 42. vref accuracy vs. load clock input considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to clock duty cycle. commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9237 contains a clock duty cycle stabilizer (dcs) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9237. as shown in figure 17 , noise and distortion performance are nearly flat over a 30% range of duty cycle with the dcs enabled. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the dll to acquire and lock to the new rate. high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f input ) due only to rms aperture jitter (t j ) can be calculated by ? ? ? ? ? ? ? ? = 2 1 20 10 in this equation, the rms aperture jitter represents the root- sum-square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. undersampling applications are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the ad9237. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (such as gating, dividing, or other methods), then it should be retimed by the original clock at the last step. the lowest typical conversion rate of the ad9237 is 1 msps. at clock rates below 1 msps, dynamic performance may degrade. power dissipation, power scaling, and standb mode as shown in figure 43 , the power dissipated by the ad9237 is proportional to its sample rate. the digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current can be calculated as nfcvi clk load drvdd drvdd = where n is 12, the number of output bits.
ad9237 rev. a | page 20 of 24 this maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the nyquist frequency, f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal. sample rate (msps) power (mw) 190 170 150 130 110 90 70 10 60 65 50 40 30 20 05455-047 ad9237-65 ad9237-40 ad9237-20 figure 43. total power vs. sample rate with f in = 10 mhz for the ad9237-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. the data in figure 43 was taken with a 5 pf load on each output driver. the ad9237 is designed to provide excellent performance with minimum power. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency, as shown in figure 43 . the power scaling feature provides an additional power savings when enabled, as shown in figure 44 . the power scaling mode cannot be enabled if the clock is varied during operation. this is because the internal circuitry cannot quickly track a changing clock, and the part does not have enough power to operate properly. sample rate (msps) power (mw) 190 170 150 130 110 90 70 10 60 65 50 40 30 20 05455-096 ad9237-65 ad9237-40 ad9237-20 figure 44. total power vs. sample rate with power scaling enabled the mode2 pin is a multilevel input that controls the span factor and power scaling modes. the mode2 pin is internally pulled down to agnd by a 70 k resistor. the input threshold and corresponding mode selections are outlined in table 8 . table 8. mode2 selection mode2 voltage span factor power scaling avdd 1 disabled 2/3 avdd 1 enabled 1/3 avdd 2 enabled agnd (default) 2 disabled the pdwn pin is a multilevel input that controls the power states. the input threshold values and corresponding power states are outlined in table 9 . table 9. pdwn selection pdwn voltage power state power (mw) avdd power-down mode 1 1/3 avdd standby mode 20 agnd (default) normal operation based on speed grade by asserting the pdwn pin high, the ad9237 is placed in power-down mode. in this state, the adc typically dissipates 1 mw. during power-down, the output drivers are placed in a high impedance state. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, clock, and duty cycle stabilizer circuitry. the decoupling capacitors on reft and refb are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in power-down mode and shorter standby cycles result in proportionally shorter wake-up times. with the recommended 0.1 f and 10 f decoupling capacitors on reft and refb, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation.
ad9237 rev. a | page 21 of 24 by asserting the pdwn pin to avdd/3, the ad9237 is placed in standby mode. in this state, the adc typically dissipates 20 mw. the output drivers are placed in a high impedance state. the reference circuitry is enabled, allowing for a quick start upon bringing the adc into normal operating mode. digital outputs the ad9237 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that can affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9237; these transients can detract from the converters dynamic performance. as detailed in table 10 , the data format can be selected for either offset binary, twos complement, or gray code. operational mode selection the ad9237 can output data in either offset binary, twos complement, or gray code format. there is also a provision for enabling or disabling the duty cycle stabilizer (dcs). the mode pin is a multilevel input that controls the data format (except for gray code) and dcs state. the mode pin is internally pulled down to agnd by a 70 k resistor. the input threshold values and corresponding mode selections are outlined in tabl e 10 . the gray code output format is obtained by connecting gc to avdd. when the part is in gray code mode, the mode pin controls the dcs function only. the gc pin is internally pulled down to agnd by a 70 k resistor. table 10. mode selection mode voltage data format duty cycle stabilizer avdd twos complement disabled 2/3 avdd twos complement enabled 1/3 avdd offset binary enabled agnd (default) offset binary disabled out of range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. the otr pin is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. therefore, the otr pin has the same pipeline latency as the digital data. otr is low when the analog input voltage is within the analog input range, and high when the analog input voltage exceeds the input range, as shown in figure 45 . otr remains high until the analog input returns to within the input range and another conversion is completed. by logically and-ing otr with the msb and its complement, overrange high or underrange low conditions can be detected. table 11 is a truth table for the overrange/ under- range circuit in figure 46 , which uses nand gates. systems requiring programmable gain condition of the ad9237 can, after eight clock cycles, detect an out-of-range condition; therefore, eliminating gain selection iterations. in addition, otr can be used for digital offset and gain calculation. 05455-049 ?fs ? 1/2 lsb otr ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb +fs ? 1 lsb +fs 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 0 0000 0000 0001 0 0000 0000 0000 0 0000 0000 0000 otr data output s figure 45. otr relation to input voltage and output data table 11. output data format otr msb analog input is 0 0 within range 0 1 within range 1 0 underrange 1 1 overrange 05455-050 msb otr msb over = 1 under = 1 figure 46. overrang e/underrange logic digital output enable function (oe) the ad9237 has three-state ability. the oe pin is internally pulled down to agnd by a 70 k resistor. if the oe pin is low, the output data drivers are enabled. if the oe pin is high, the output data drivers are placed in a high impedance state. it is not intended for rapid access to the data bus. note that the oe pin is referenced to the digital supplies (drvdd) and should not exceed that voltage. timing the ad9237 provides latched data outputs with a pipeline delay of eight clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. refer to figure 2 for a detailed timing diagram.
ad9237 rev. a | page 22 of 24 outline dimensions compliant to jedec standards mo-220-vhhd-2 011708-a 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indi c ator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 47. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 , temperature range package description package option AD9237BCPZ-20 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad9237bcpzrl7-20 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad9237bcpz-40 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad9237bcpzrl7-40 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad9237bcpz-65 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad9237bcpzrl7-65 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 1 z = rohs-compliant part.
ad9237 rev. a | page 23 of 24 notes
ad9237 rev. a | page 24 of 24 notes ? 2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05455C0C5 /10(a)

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